Memory devices are typically often provided as internal storage areas in a computer, such as in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost, whereas ROM is non-volatile and retains its data when power is lost.
Dynamic RAM (DRAM) and synchronous DRAM (SDRAM) are types of RAM wherein the data is typically stored as individual charges (or lack thereof) placed in memory cells formed from capacitors coupled to select gate transistors in the DRAM memory array. To access and read the data the select gates coupled to the selected memory cells are activated and the charge stored on the associated memory cell capacitors are coupled to bit lines and the stored values are read by sense amplifiers. As this data read removes the charge stored in the selected memory cell capacitors the data must then be rewritten back into the selected cells so that it is available for any future access. In addition, as the memory cell capacitors typically slowly leak charge, the charges on the capacitors of the array must be periodically refreshed by being read and written back into the cell in a refresh operation, maintaining the data contents. This refresh operation can be executed either by the host, typically a processor or memory controller coupled to the memory, or by an onboard controller or control state machine of the DRAM in a “self-refresh” operation.
Low Power Dynamic Random Access Memory (LPDRAM) and Low Power Synchronous Dynamic Random Access Memory (LPSDRAM), both referred to herein as LPDRAM, are similar in operation and structure to conventional asynchronous and synchronous DRAM devices, but includes features designed to reduce power consumption in several modes of operation and/or adjustments. In particular, the operation of self-refresh mode of a DRAM can draw a relatively high amount of power to refresh the data in its memory array. As a result, LPDRAM allows for the adjustability of the self-refresh operation and, in particular, its repetition rate (also known as the repetition frequency), through any of a variety of mechanisms to allow the power draw of this operation to be reduced in LPDRAM. Because of this, LPDRAM is typically utilized in battery powered or other low power environments.
A problem in modern LPDRAM memory devices is that configuring a LPDRAM for low power operation, is difficult and highly dependent on the environmental conditions internal and external to the LPDRAM. In particular, the selection of the self-refresh timing and repetition frequency is highly dependant on the operating temperature of the LPDRAM and the available power supply voltage in establishing the settings and repetition frequency that maximizes power savings and yet still maintains the data state of the memory cells. Conventional DRAM memory devices avoid this problem by utilizing higher power usage settings, such as by refreshing at a rate higher than required for the memory operating environment and temperature. Because of this sensitivity, configuration of the LPDRAM is typically done by the controller or processor coupled to the LPDRAM utilizing routines, which as used here can include linkable libraries given to the designer/end-user/system manufacturer by the LPDRAM manufacturer. These routines are typically supplied in a source code format or as a linkable library and, as such, must be compiled into the operating system or overall code executing on the device. As these routines add complexity to the system design process and operating software they add additional design and testing complexity, and if not implemented correctly can cause data corruption and/or system failure, in particular, when the system is operating in extreme environmental conditions, such as in extreme voltages and temperatures. In addition, these LPDRAM routines can also differ by manufacturer, LPDRAM type and/or revision, causing potential issues with future compatibility and parts availability as new LPDRAM's are developed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods of configuring LPDRAM memory devices and arrays.